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sci-electronics/verilator: add upstream to metadata.xml

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Add github remote-id verilator/verilator

Package-Manager: Portage-2.3.96, Repoman-2.3.22
Signed-off-by: Huang Rui <vowstar@gmail.com>
This commit is contained in:
Huang Rui
2020-04-07 16:01:32 +08:00
parent 73826d7a53
commit eb6f3704b1
1 changed files with 3 additions and 0 deletions
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sci-electronics/verilator/metadata.xml
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@@ -5,6 +5,9 @@
<email>vowstar@gmail.com</email> <email>vowstar@gmail.com</email>
<name>Huang Rui</name> <name>Huang Rui</name>
</maintainer> </maintainer>
<upstream>
<remote-id type="github">verilator/verilator</remote-id>
</upstream>
<longdescription> <longdescription>
Verilator, the fastest free Verilog HDL simulator. Verilator, the fastest free Verilog HDL simulator.
Accepts synthesizable Verilog or SystemVerilog Accepts synthesizable Verilog or SystemVerilog