From eb6f3704b14ff8a2dd909ffd406887e605bbd3af Mon Sep 17 00:00:00 2001
From: Huang Rui <vowstar@gmail.com>
Date: Tue, 7 Apr 2020 16:01:32 +0800
Subject: [PATCH] sci-electronics/verilator: add upstream to metadata.xml

Add github remote-id verilator/verilator

Package-Manager: Portage-2.3.96, Repoman-2.3.22
Signed-off-by: Huang Rui <vowstar@gmail.com>
---
 sci-electronics/verilator/metadata.xml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sci-electronics/verilator/metadata.xml b/sci-electronics/verilator/metadata.xml
index 626ddc8c86..7756cca212 100644
--- a/sci-electronics/verilator/metadata.xml
+++ b/sci-electronics/verilator/metadata.xml
@@ -5,6 +5,9 @@
 		<email>vowstar@gmail.com</email>
 		<name>Huang Rui</name>
 	</maintainer>
+	<upstream>
+		<remote-id type="github">verilator/verilator</remote-id>
+	</upstream>
 	<longdescription>
 	Verilator, the fastest free Verilog HDL simulator.
 	Accepts synthesizable Verilog or SystemVerilog