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sci-electronics/circt: enable py3.12 and disable py3.10

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Signed-off-by: Yuhang Zeng <unlsycn@unlsycn.com>
This commit is contained in:
Yuhang Zeng
2024-06-13 00:29:47 +08:00
parent a9ac3703f6
commit fe47557fba
2 changed files with 2 additions and 2 deletions
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2
sci-electronics/circt/circt-1.14.0.ebuild
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@@ -6,7 +6,7 @@ EAPI="8"
MY_PV="${PV//./\/}"
MY_LLVM_PV="fe0f72d5c55a9b95c5564089e946e8f08112e995"
CMAKE_BUILD_TYPE="Release"
PYTHON_COMPAT=( python3_{10..11} )
PYTHON_COMPAT=( python3_{11..12} )
inherit cmake python-r1
DESCRIPTION="The fast free Verilog/SystemVerilog simulator"

2
sci-electronics/circt/circt-1.37.0.ebuild
View File

@@ -6,7 +6,7 @@ EAPI="8"
MY_PV="${PV//./\/}"
MY_LLVM_PV="d978730d8e2c10c76867b83bec2f1143d895ee7d"
CMAKE_BUILD_TYPE="Release"
PYTHON_COMPAT=( python3_{10..11} )
PYTHON_COMPAT=( python3_{11..12} )
inherit cmake python-r1
DESCRIPTION="The fast free Verilog/SystemVerilog simulator"