From fe47557fbada13a64eacab72846fd49a0530959f Mon Sep 17 00:00:00 2001 From: Yuhang Zeng Date: Thu, 13 Jun 2024 00:29:47 +0800 Subject: [PATCH] sci-electronics/circt: enable py3.12 and disable py3.10 Signed-off-by: Yuhang Zeng --- sci-electronics/circt/circt-1.14.0.ebuild | 2 +- sci-electronics/circt/circt-1.37.0.ebuild | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sci-electronics/circt/circt-1.14.0.ebuild b/sci-electronics/circt/circt-1.14.0.ebuild index 181b5b44f6..42854ef961 100644 --- a/sci-electronics/circt/circt-1.14.0.ebuild +++ b/sci-electronics/circt/circt-1.14.0.ebuild @@ -6,7 +6,7 @@ EAPI="8" MY_PV="${PV//./\/}" MY_LLVM_PV="fe0f72d5c55a9b95c5564089e946e8f08112e995" CMAKE_BUILD_TYPE="Release" -PYTHON_COMPAT=( python3_{10..11} ) +PYTHON_COMPAT=( python3_{11..12} ) inherit cmake python-r1 DESCRIPTION="The fast free Verilog/SystemVerilog simulator" diff --git a/sci-electronics/circt/circt-1.37.0.ebuild b/sci-electronics/circt/circt-1.37.0.ebuild index ce9f7c46be..0b1a877e51 100644 --- a/sci-electronics/circt/circt-1.37.0.ebuild +++ b/sci-electronics/circt/circt-1.37.0.ebuild @@ -6,7 +6,7 @@ EAPI="8" MY_PV="${PV//./\/}" MY_LLVM_PV="d978730d8e2c10c76867b83bec2f1143d895ee7d" CMAKE_BUILD_TYPE="Release" -PYTHON_COMPAT=( python3_{10..11} ) +PYTHON_COMPAT=( python3_{11..12} ) inherit cmake python-r1 DESCRIPTION="The fast free Verilog/SystemVerilog simulator"