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https://github.com/gentoo-mirror/guru.git
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2024-02-24 13:03:16 UTC
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BDEPEND=app-arch/unzip sys-devel/bison sys-devel/flex sys-devel/m4 >=dev-build/bazel-0.20
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DEFINED_PHASES=compile install prepare test unpack
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DEPEND=sys-libs/zlib
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DESCRIPTION=SystemVerilog parser, style-linter, and formatter
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EAPI=8
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INHERIT=bazel
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IUSE=test
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KEYWORDS=~amd64
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LICENSE=Apache-2.0
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RDEPEND=sys-libs/zlib
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RESTRICT=!test? ( test )
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SLOT=0
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@@ -1,16 +0,0 @@
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BDEPEND=app-arch/unzip sys-devel/bison sys-devel/flex sys-devel/m4 >=dev-build/bazel-0.20
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DEPEND=sys-libs/zlib
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DESCRIPTION=SystemVerilog parser, style-linter, and formatter
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EAPI=8
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HOMEPAGE=https://chipsalliance.github.io/verible/ https://github.com/chipsalliance/verible
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INHERIT=bazel
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IUSE=test
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KEYWORDS=~amd64
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LICENSE=Apache-2.0
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RDEPEND=sys-libs/zlib
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RESTRICT=!test? ( test )
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SLOT=0
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_eclasses_=multiprocessing 30ead54fa2e2b5f9cd4e612ffc34d0fe toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 bazel 01fa853437e158c237a22fdf3d43f365
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_md5_=5cb631a37b96626365e941540a017d54
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@@ -1881,7 +1881,6 @@ sci-electronics/open_pdks 1.0.311: PDK installer for open-source EDA tools and t
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sci-electronics/skywater-pdk 0.0.0_p20220424: Process design kit for usage with SkyWater Technology Foundry's 130nm node
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sci-electronics/slang 1.0 2.0-r2 3.0 4.0 5.0 9999: SystemVerilog compiler and language services
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sci-electronics/svls 0.2.11: SystemVerilog language server
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sci-electronics/verible 0.0.3420 0.0.3430: SystemVerilog parser, style-linter, and formatter
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sci-electronics/verilator 4.106 5.014 5.018 9999: The fast free Verilog/SystemVerilog simulator
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sci-geosciences/GeographicLib-data 0-r1: Datasets for GeographicLib
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sci-libs/ButterflyPACK 2.1.1-r1: Mathematical software for solving large-scale dense linear systems
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@@ -1 +1 @@
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Sat, 24 Feb 2024 12:20:07 +0000
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Sat, 24 Feb 2024 13:03:16 +0000
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