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2024-04-30 18:33:19 UTC

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2024-04-30 18:33:19 +00:00
parent 92e386e979
commit 66602dbc4b
4 changed files with 3 additions and 15 deletions
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metadata/md5-cache/sci-electronics/yosys-0.32
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BDEPEND=dev-vcs/git
DEFINED_PHASES=install prepare
DEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=http://www.clifford.at/yosys/
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/archive/yosys-0.32.tar.gz https://github.com/YosysHQ/abc/archive/bb64142b07794ee685494564471e67365a093710.tar.gz -> abc-bb64142b07794ee685494564471e67365a093710.tar.gz
_md5_=9c8a43f1fbffe94d80e8488434172d6a