diff --git a/metadata/md5-cache/dev-scheme/sagittarius-0.9.11 b/metadata/md5-cache/dev-scheme/sagittarius-0.9.11
index 940ac46370..6f3535613f 100644
--- a/metadata/md5-cache/dev-scheme/sagittarius-0.9.11
+++ b/metadata/md5-cache/dev-scheme/sagittarius-0.9.11
@@ -11,4 +11,4 @@ RDEPEND=dev-libs/boehm-gc dev-libs/libffi dev-libs/openssl sys-libs/zlib
 SLOT=0
 SRC_URI=https://bitbucket.org/ktakashi/sagittarius-scheme/downloads/sagittarius-0.9.11.tar.gz
 _eclasses_=toolchain-funcs	e56c7649b804f051623c8bc1a1c44084	multilib	c19072c3cd7ac5cb21de013f7e9832e0	flag-o-matic	288c54efeb5e2aa70775e39032695ad4	multiprocessing	30ead54fa2e2b5f9cd4e612ffc34d0fe	ninja-utils	2df4e452cea39a9ec8fb543ce059f8d6	xdg-utils	baea6080dd821f5562d715887954c9d3	cmake	c7c9a62d6232cac66d4ea32d575c3e7c	edo	c0eb9cbe6b0bd01fcb4918f12598a4d3
-_md5_=985a6b3d4208ccabef905b461c061e0a
+_md5_=cc75c0043381e078964ae13aea17695d
diff --git a/metadata/md5-cache/sci-electronics/yosys-0.32 b/metadata/md5-cache/sci-electronics/yosys-0.32
deleted file mode 100644
index 8626f6708d..0000000000
--- a/metadata/md5-cache/sci-electronics/yosys-0.32
+++ /dev/null
@@ -1,12 +0,0 @@
-BDEPEND=dev-vcs/git
-DEFINED_PHASES=install prepare
-DEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
-DESCRIPTION=framework for Verilog RTL synthesis
-EAPI=8
-HOMEPAGE=http://www.clifford.at/yosys/
-KEYWORDS=~amd64
-LICENSE=ISC
-RDEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
-SLOT=0
-SRC_URI=https://github.com/YosysHQ/yosys/archive/yosys-0.32.tar.gz https://github.com/YosysHQ/abc/archive/bb64142b07794ee685494564471e67365a093710.tar.gz -> abc-bb64142b07794ee685494564471e67365a093710.tar.gz
-_md5_=9c8a43f1fbffe94d80e8488434172d6a
diff --git a/metadata/pkg_desc_index b/metadata/pkg_desc_index
index 673713828e..70f68ad147 100644
--- a/metadata/pkg_desc_index
+++ b/metadata/pkg_desc_index
@@ -1492,7 +1492,7 @@ sci-electronics/skywater-pdk 0.0.0_p20220424: Process design kit for usage with
 sci-electronics/slang 4.0 5.0 6.0 9999: SystemVerilog compiler and language services
 sci-electronics/svls 0.2.11: SystemVerilog language server
 sci-electronics/verilator 5.022 5.024 9999: The fast free Verilog/SystemVerilog simulator
-sci-electronics/yosys 0.32 0.40: framework for Verilog RTL synthesis
+sci-electronics/yosys 0.40: framework for Verilog RTL synthesis
 sci-mathematics/frama-c 23.1-r1 24.0-r1 25.0-r2: Framework for analysis of source codes written in C
 sci-mathematics/frama-c-aorai 23.1 24.0 25.0: Aorai (automaton annotations) plugin for frama-c
 sci-mathematics/frama-c-callgraph 23.1 24.0 25.0: Callgraph plugin for frama-c
diff --git a/metadata/timestamp.chk b/metadata/timestamp.chk
index 890047a140..da18355b61 100644
--- a/metadata/timestamp.chk
+++ b/metadata/timestamp.chk
@@ -1 +1 @@
-Tue, 30 Apr 2024 12:33:29 +0000
+Tue, 30 Apr 2024 18:33:19 +0000