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guru/metadata/md5-cache/sci-electronics/yosys-0.61-r1
Repository mirror & CI 47d7585cfe 2026-02-03 23:33:11 UTC
2026-02-03 23:33:11 +00:00

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BDEPEND=|| ( dev-lang/python:3.14 dev-lang/python:3.13 dev-lang/python:3.12 dev-lang/python:3.11 ) dev-vcs/git virtual/pkgconfig
DEFINED_PHASES=configure prepare setup
DEPEND=dev-libs/boost:= dev-libs/libffi:= dev-lang/tcl:= llvm_slot_18? ( llvm-core/clang:18= ) llvm_slot_19? ( llvm-core/clang:19= ) llvm_slot_20? ( llvm-core/clang:20= ) llvm_slot_21? ( llvm-core/clang:21= ) media-gfx/xdot sys-libs/ncurses:= sys-libs/readline:= virtual/zlib
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=https://yosyshq.net/yosys/
INHERIT=python-any-r1 llvm-r2
IUSE=+llvm_slot_21 llvm_slot_18 llvm_slot_19 llvm_slot_20
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost:= dev-libs/libffi:= dev-lang/tcl:= llvm_slot_18? ( llvm-core/clang:18= ) llvm_slot_19? ( llvm-core/clang:19= ) llvm_slot_20? ( llvm-core/clang:20= ) llvm_slot_21? ( llvm-core/clang:21= ) media-gfx/xdot sys-libs/ncurses:= sys-libs/readline:= virtual/zlib
REQUIRED_USE=^^ ( llvm_slot_18 llvm_slot_19 llvm_slot_20 llvm_slot_21 )
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/releases/download/v0.61/yosys.tar.gz -> yosys-0.61.tar.gz
_eclasses_=multiprocessing 1e32df7deee68372153dca65f4a7c21f toolchain-funcs 7e440a20ac11dece04e3334622e6e5da python-utils-r1 dbb8c4d794033ad7e7221eaf567a6c90 python-any-r1 891415dfe39ad9b41b461f2b86354af0 llvm-utils e7edb4086e31c8537574b263d899f826 multilib 404b65bd5212cff83b3935c685419d08 llvm-r2 d6b14d3bbccc5ab5b4182c606245dbd3
_md5_=4d3b5ab5e4db3b4928ee2f38bf3aa92e