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18 lines
1.9 KiB
Plaintext
18 lines
1.9 KiB
Plaintext
BDEPEND=virtual/pkgconfig >=dev-util/ninja-1.8.2 >=dev-util/cmake-3.20.5
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DEFINED_PHASES=compile configure install prepare test
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DEPEND=python_targets_python3_10? ( >=dev-lang/python-3.10.9-r1:3.10 ) python_targets_python3_11? ( >=dev-lang/python-3.11.1-r1:3.11 ) test? ( dev-python/psutil[python_targets_python3_10(-)?,python_targets_python3_11(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
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DESCRIPTION=The fast free Verilog/SystemVerilog simulator
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EAPI=8
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HOMEPAGE=https://circt.llvm.org https://github.com/llvm/circt
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INHERIT=cmake python-r1
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IUSE=test python_targets_python3_10 python_targets_python3_11
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KEYWORDS=~amd64 ~arm64 ~riscv ~x86
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LICENSE=Apache-2.0-with-LLVM-exceptions UoI-NCSA BSD public-domain rc
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RDEPEND=python_targets_python3_10? ( >=dev-lang/python-3.10.9-r1:3.10 ) python_targets_python3_11? ( >=dev-lang/python-3.11.1-r1:3.11 ) test? ( dev-python/psutil[python_targets_python3_10(-)?,python_targets_python3_11(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
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REQUIRED_USE=|| ( python_targets_python3_10 python_targets_python3_11 )
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RESTRICT=!test? ( test )
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SLOT=0
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SRC_URI=https://github.com/llvm/circt/archive/refs/tags/sifive/1/14/0.tar.gz -> circt-1.14.0.tar.gz https://github.com/llvm/llvm-project/archive/fe0f72d5c55a9b95c5564089e946e8f08112e995.tar.gz -> llvm-project-fe0f72d5c55a9b95c5564089e946e8f08112e995.tar.gz
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_eclasses_=toolchain-funcs 14a8ae365191b518fad51caad7a08f3e multilib 104e1332efb829e2f7cbf89307a474f1 flag-o-matic 16483e58fadb0d47b4528f0aa7e171f6 multiprocessing b4e253ab22cef7b1085e9b67c7a3b730 ninja-utils 76050953ad5b70d7e09a6ca55558db92 xdg-utils baea6080dd821f5562d715887954c9d3 cmake 7fb5980de96325cbab639f5b2187357c out-of-source-utils 1a9007554652a6e627edbccb3c25a439 multibuild bddcb51b74f4a76724ff7cf8e7388869 python-utils-r1 0857e21aa6e0f3748cfd8829a98ce1f7 python-r1 3c6cd0f418ba702c186a9865b85e704d
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_md5_=834456c7dd1c140b048ba5ad2954d58e
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