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guru/metadata/md5-cache/sci-electronics/circt-1.37.0
Repository mirror & CI 503f61e56d 2023-07-22 00:03:50 UTC
2023-07-22 00:03:50 +00:00

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BDEPEND=virtual/pkgconfig >=dev-util/ninja-1.8.2 >=dev-util/cmake-3.20.5
DEFINED_PHASES=compile configure install prepare test
DEPEND=python_targets_python3_10? ( dev-lang/python:3.10 ) python_targets_python3_11? ( dev-lang/python:3.11 ) test? ( dev-python/psutil[python_targets_python3_10(-)?,python_targets_python3_11(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
HOMEPAGE=https://circt.llvm.org https://github.com/llvm/circt
INHERIT=cmake python-r1
IUSE=test python_targets_python3_10 python_targets_python3_11
KEYWORDS=~amd64 ~arm64 ~riscv ~x86
LICENSE=Apache-2.0-with-LLVM-exceptions UoI-NCSA BSD public-domain rc
RDEPEND=python_targets_python3_10? ( dev-lang/python:3.10 ) python_targets_python3_11? ( dev-lang/python:3.11 ) test? ( dev-python/psutil[python_targets_python3_10(-)?,python_targets_python3_11(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
REQUIRED_USE=|| ( python_targets_python3_10 python_targets_python3_11 )
RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/llvm/circt/archive/refs/tags/firtool-1.37.0.tar.gz -> circt-1.37.0.tar.gz https://github.com/llvm/llvm-project/archive/d978730d8e2c10c76867b83bec2f1143d895ee7d.tar.gz -> llvm-project-d978730d8e2c10c76867b83bec2f1143d895ee7d.tar.gz
_eclasses_=toolchain-funcs 8e3fb781f3258ae2757d1dfc2c7c170e multilib c19072c3cd7ac5cb21de013f7e9832e0 flag-o-matic ad475baa777c9978fa035216c8264a10 multiprocessing b4e253ab22cef7b1085e9b67c7a3b730 ninja-utils f3010c780f65d1bb5aea15a9af1adc9c xdg-utils baea6080dd821f5562d715887954c9d3 cmake aa1d1fa7be37663d48162ac963b22692 out-of-source-utils 1a9007554652a6e627edbccb3c25a439 multibuild 30dbf3c5a31db09a19f31ad0a68f2405 python-utils-r1 7661dc585f75dd1f81eccefe37bef093 python-r1 b3f874304c1bda6ffc3450ebb4ae5169
_md5_=57f99aa6b4a9406d02b9de1f47a7c1f1