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guru/metadata/md5-cache/sci-electronics/yosys-0.63
Repository mirror & CI 092b30a0d5 2026-03-30 13:31:48 UTC
2026-03-30 13:31:48 +00:00

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BDEPEND=|| ( dev-lang/python:3.14 dev-lang/python:3.13 dev-lang/python:3.12 ) dev-vcs/git virtual/pkgconfig
DEFINED_PHASES=configure prepare setup
DEPEND=dev-libs/boost:= dev-libs/libffi:= dev-lang/tcl:= llvm_slot_18? ( llvm-core/clang:18= ) llvm_slot_19? ( llvm-core/clang:19= ) llvm_slot_20? ( llvm-core/clang:20= ) llvm_slot_21? ( llvm-core/clang:21= ) media-gfx/xdot sys-libs/ncurses:= sys-libs/readline:= virtual/zlib
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=https://yosyshq.net/yosys/
INHERIT=python-any-r1 llvm-r2
IUSE=+llvm_slot_21 llvm_slot_18 llvm_slot_19 llvm_slot_20
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost:= dev-libs/libffi:= dev-lang/tcl:= llvm_slot_18? ( llvm-core/clang:18= ) llvm_slot_19? ( llvm-core/clang:19= ) llvm_slot_20? ( llvm-core/clang:20= ) llvm_slot_21? ( llvm-core/clang:21= ) media-gfx/xdot sys-libs/ncurses:= sys-libs/readline:= virtual/zlib
REQUIRED_USE=^^ ( llvm_slot_18 llvm_slot_19 llvm_slot_20 llvm_slot_21 )
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/releases/download/v0.63/yosys.tar.gz -> yosys-0.63.tar.gz
_eclasses_=eapi9-pipestatus d2c134036ac31c3085aebc9147f572bd multiprocessing 45d0620f25c2f063ad6276ecd9ed9399 toolchain-funcs 5195689ff6a73b0e789acfa09d4fbcb9 python-utils-r1 9c4180f103a0e8340bc993fc85dbdadd python-any-r1 891415dfe39ad9b41b461f2b86354af0 llvm-utils e7edb4086e31c8537574b263d899f826 multilib fc812e8eb2170022c28272d80a1f9e77 llvm-r2 8bc46809768366b4239eab39335419bc
_md5_=9d34cc014e25d7bc7abb23a74059343f