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guru/metadata/md5-cache/sci-electronics/circt-1.76.0
Repository mirror & CI 30a2e09178 2024-08-19 06:22:56 UTC
2024-08-19 06:22:56 +00:00

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BDEPEND=virtual/pkgconfig app-alternatives/ninja >=dev-build/cmake-3.20.5
DEFINED_PHASES=compile configure install prepare test
DEPEND=python_targets_python3_11? ( dev-lang/python:3.11 ) python_targets_python3_12? ( dev-lang/python:3.12 ) test? ( dev-python/psutil[python_targets_python3_11(-)?,python_targets_python3_12(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
HOMEPAGE=https://circt.llvm.org https://github.com/llvm/circt
INHERIT=cmake python-r1
IUSE=test python_targets_python3_11 python_targets_python3_12
KEYWORDS=~amd64 ~arm64 ~riscv ~x86
LICENSE=Apache-2.0-with-LLVM-exceptions UoI-NCSA BSD public-domain rc
RDEPEND=python_targets_python3_11? ( dev-lang/python:3.11 ) python_targets_python3_12? ( dev-lang/python:3.12 ) test? ( dev-python/psutil[python_targets_python3_11(-)?,python_targets_python3_12(-)?] sci-electronics/verilator ) sys-libs/ncurses:0=
REQUIRED_USE=|| ( python_targets_python3_11 python_targets_python3_12 )
RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/llvm/circt/archive/refs/tags/firtool-1.76.0.tar.gz -> circt-1.76.0.tar.gz https://github.com/llvm/llvm-project/archive/6595e7fa1b5588f860aa057aac47c43623169584.tar.gz -> llvm-project-6595e7fa1b5588f860aa057aac47c43623169584.tar.gz
_eclasses_=toolchain-funcs 333970c740aa7b1a92e4fcdc52f612bd multilib c19072c3cd7ac5cb21de013f7e9832e0 flag-o-matic e503ea5acc20410237ba33ec3f7c857d multiprocessing 30ead54fa2e2b5f9cd4e612ffc34d0fe ninja-utils 2df4e452cea39a9ec8fb543ce059f8d6 xdg-utils baea6080dd821f5562d715887954c9d3 cmake 10a50dfaf728b802fcfd37f8d0da9056 out-of-source-utils 1a9007554652a6e627edbccb3c25a439 multibuild d67e78a235f541871c7dfe4cf7931489 python-utils-r1 6881b056477c23167d9a6b33e146374e python-r1 c1fc393cd1e72f093b4838e29d27918c
_md5_=65ae3d33723f276c82a1ad2e09396276