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32 lines
1.5 KiB
XML
32 lines
1.5 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE pkgmetadata SYSTEM "https://www.gentoo.org/dtd/metadata.dtd">
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<pkgmetadata>
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<maintainer type="person">
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<email>vowstar@gmail.com</email>
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<name>Huang Rui</name>
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</maintainer>
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<upstream>
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<remote-id type="github">chipsalliance/verible</remote-id>
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</upstream>
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<longdescription lang="en">
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Verible is a suite of SystemVerilog developer tools, including a parser,
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style-linter, and formatter.
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The Verible project's main mission is to parse SystemVerilog
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(IEEE 1800-2017) (as standardized in the SV-LRM) for a wide variety of
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applications, including developer tools.
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It was born out of a need to parse un-preprocessed source files, which is
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suitable for single-file applications like style-linting and formatting.
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In doing so, it can be adapted to parse preprocessed source files, which is
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what real compilers and toolchains require.
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The spirit of the project is that no-one should ever have to develop a
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SystemVerilog parser for their own application, because developing a
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standard-compliant parser is an enormous task due to the syntactic
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complexity of the language. Verible's parser is also regularly tested
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against an ever-growing suite of (tool-independent) language compliance
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tests at https://symbiflow.github.io/sv-tests/.
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A lesser (but notable) objective is that the language-agnostic components
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of Verible be usable for rapidly developing language support tools for
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other languages.
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</longdescription>
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</pkgmetadata>
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