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2020-05-14 09:34:59 UTC

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2020-05-14 09:34:59 +00:00
parent 324d919432
commit fd2af226b2
12 changed files with 31 additions and 32 deletions
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6
metadata/md5-cache/sci-electronics/verilator-4.034
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@@ -3,11 +3,11 @@ DEFINED_PHASES=prepare
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=7
HOMEPAGE=https://www.veripool.org/wiki/verilator
HOMEPAGE=https://verilator.org https://github.com/verilator/verilator
KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86
LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=http://www.veripool.org/ftp/verilator-4.034.tgz -> verilator-4.034.tar.gz
SRC_URI=https://github.com/verilator/verilator/archive/v4.034.tar.gz -> verilator-4.034.tar.gz
_eclasses_=autotools 7d999b62b8749fad43fff00620cedf47 libtool f143db5a74ccd9ca28c1234deffede96 multilib 318e8ae683e57fd3ccd0d31a769d8ee8 toolchain-funcs 512eb3367f507ebaa1d1d43ab7d66e6c
_md5_=66f8f02f5cb2cbfdd10193b69c90261a
_md5_=daf1fe3e48c8ad5d5fe1f017b86b6c87

4
metadata/md5-cache/sci-electronics/verilator-9999
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@@ -3,10 +3,10 @@ DEFINED_PHASES=prepare unpack
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=7
HOMEPAGE=https://www.veripool.org/wiki/verilator
HOMEPAGE=https://verilator.org https://github.com/verilator/verilator
LICENSE=|| ( Artistic-2 LGPL-3 )
PROPERTIES=live
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
_eclasses_=autotools 7d999b62b8749fad43fff00620cedf47 git-r3 86a0188f2ad9eb3d65e4d031ab8a0422 libtool f143db5a74ccd9ca28c1234deffede96 multilib 318e8ae683e57fd3ccd0d31a769d8ee8 toolchain-funcs 512eb3367f507ebaa1d1d43ab7d66e6c
_md5_=66f8f02f5cb2cbfdd10193b69c90261a
_md5_=7c52df605cf857c0dd5c13e199ce4705