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2025-12-07 11:15:53 UTC

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2025-12-07 11:15:53 +00:00
parent 6bcf2f5918
commit f0d166b784
71 changed files with 424 additions and 294 deletions
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15
metadata/md5-cache/sci-electronics/sby-0.60 Normal file
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@@ -0,0 +1,15 @@
DEFINED_PHASES=install setup
DEPEND=python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) python_single_target_python3_14? ( dev-lang/python:3.14 ) python_single_target_python3_11? ( dev-python/click[python_targets_python3_11(-)] ) python_single_target_python3_12? ( dev-python/click[python_targets_python3_12(-)] ) python_single_target_python3_13? ( dev-python/click[python_targets_python3_13(-)] ) python_single_target_python3_14? ( dev-python/click[python_targets_python3_14(-)] ) sci-electronics/yosys sci-mathematics/z3 yices2? ( sci-mathematics/yices2 )
DESCRIPTION=Front-end for Yosys-based formal hardware verification flows
EAPI=8
HOMEPAGE=https://github.com/YosysHQ/sby
INHERIT=python-single-r1
IUSE=yices2 python_single_target_python3_11 python_single_target_python3_12 python_single_target_python3_13 python_single_target_python3_14
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) python_single_target_python3_14? ( dev-lang/python:3.14 ) python_single_target_python3_11? ( dev-python/click[python_targets_python3_11(-)] ) python_single_target_python3_12? ( dev-python/click[python_targets_python3_12(-)] ) python_single_target_python3_13? ( dev-python/click[python_targets_python3_13(-)] ) python_single_target_python3_14? ( dev-python/click[python_targets_python3_14(-)] ) sci-electronics/yosys sci-mathematics/z3 yices2? ( sci-mathematics/yices2 )
REQUIRED_USE=^^ ( python_single_target_python3_11 python_single_target_python3_12 python_single_target_python3_13 python_single_target_python3_14 )
SLOT=0
SRC_URI=https://github.com/YosysHQ/sby/archive/v0.60.tar.gz -> sby-0.60.tar.gz
_eclasses_=multiprocessing 1e32df7deee68372153dca65f4a7c21f toolchain-funcs 98d9f464d912ae6b7316fb8a3721f5db python-utils-r1 dbb8c4d794033ad7e7221eaf567a6c90 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_md5_=69cca7a17786029ae22f9a1754d8b4f8

6
metadata/md5-cache/sci-electronics/yosys-0.57 → metadata/md5-cache/sci-electronics/yosys-0.60
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@@ -3,10 +3,10 @@ DEFINED_PHASES=configure
DEPEND=dev-libs/boost media-gfx/xdot llvm-core/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=http://www.clifford.at/yosys/
HOMEPAGE=https://yosyshq.net/yosys/
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost media-gfx/xdot llvm-core/clang
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/releases/download/v0.57/yosys.tar.gz -> yosys-0.57.tar.gz
_md5_=ebfebfdd588625e3bee0a52926b656dd
SRC_URI=https://github.com/YosysHQ/yosys/releases/download/v0.60/yosys.tar.gz -> yosys-0.60.tar.gz
_md5_=3885297d9da518b7b6d3b29c0e33826a