From f013fe6428650bafaa24252299664e3e2681ebe1 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Thu, 11 Dec 2025 14:01:51 +0800 Subject: [PATCH] sci-electronics/verilator: enable py3.14 Signed-off-by: Huang Rui --- sci-electronics/verilator/metadata.xml | 15 +++++++++------ sci-electronics/verilator/verilator-9999.ebuild | 2 +- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/sci-electronics/verilator/metadata.xml b/sci-electronics/verilator/metadata.xml index ce85e6abd1..8cbb9af065 100644 --- a/sci-electronics/verilator/metadata.xml +++ b/sci-electronics/verilator/metadata.xml @@ -9,10 +9,13 @@ verilator/verilator - Verilator, the fastest free Verilog HDL simulator. - Accepts synthesizable Verilog or SystemVerilog - Performs lint code-quality checks - Compiles into multithreaded C++, SystemC, or (soon) C++-under-Python - Creates XML to front-end your own tools + Verilator, the fastest Verilog/SystemVerilog simulator. Accepts Verilog + or SystemVerilog. Performs lint code-quality checks. Compiles into + multithreaded C++, or SystemC. Creates XML to front-end your own tools. - + + Verilator，最快的 Verilog/SystemVerilog 模拟器。支持 Verilog 和 + SystemVerilog。执行 lint 代码质量检查。可编译为多线程 C++ 或 + SystemC。生成 XML 以对接您自己的工具。 + + \ No newline at end of file diff --git a/sci-electronics/verilator/verilator-9999.ebuild b/sci-electronics/verilator/verilator-9999.ebuild index ec54ecf856..bca851bc6d 100644 --- a/sci-electronics/verilator/verilator-9999.ebuild +++ b/sci-electronics/verilator/verilator-9999.ebuild @@ -3,7 +3,7 @@ EAPI="8" -PYTHON_COMPAT=( python3_{11..13} ) +PYTHON_COMPAT=( python3_{11..14} ) inherit autotools python-single-r1