sci-electronics/yosys: add 0.65

Signed-off-by: Huang Rui <vowstar@gmail.com>

sci-electronics/yosys/Manifest

@@ -1 +1,2 @@
 DIST yosys-0.64.tar.gz 11107644 BLAKE2B ec50ee21a27d78c56e559474eeb7a9d6bc575582929855ec2ae3d4d04dd8613d8f0e8bb98a2ec6fff01b1de9ff802634ad1e5427c10b85ad82e687ebaf40c317 SHA512 34c9aee8f325a7d31be223efcc75ff2a5fc15a149fdacaa4cc629107b2e68debd1b9b8fb69f06b297a134dc6ba4e2814e0f2e2926f1eddaf09df8f0c794746ee
+DIST yosys-0.65.tar.gz 11174680 BLAKE2B 19e0026b4731d9ef176b3ac12f29b911a7c40ad2b1171f85f7bd1da38512564fdbd55e1c73255557d3153831314254f76a35ee61edf839374834a33c340555f7 SHA512 700b2659208e53a18cd90c6456ffab44ef14b6c69ad34f61840371e8eb8cebfd9b2884a4524aa77bbb7f8b8466a9655326f096b7db5ba981b2cd51d7f7dc93f5

sci-electronics/yosys/yosys-0.65.ebuild

@@ -0,0 +1,66 @@
+# Copyright 1999-2026 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=8
+
+PYTHON_COMPAT=( python3_{11..14} )
+LLVM_COMPAT=( {18..21} )
+
+inherit python-any-r1 llvm-r2
+
+DESCRIPTION="framework for Verilog RTL synthesis"
+HOMEPAGE="https://yosyshq.net/yosys/"
+SRC_URI="
+	https://github.com/YosysHQ/${PN}/releases/download/v${PV}/yosys.tar.gz -> ${P}.tar.gz
+"
+S="${WORKDIR}"
+
+LICENSE="ISC"
+SLOT="0"
+KEYWORDS="~amd64"
+RDEPEND="
+	dev-libs/boost:=
+	dev-libs/libffi:=
+	dev-lang/tcl:=
+	$(llvm_gen_dep '
+		llvm-core/clang:${LLVM_SLOT}=
+	')
+	media-gfx/xdot
+	sys-libs/ncurses:=
+	sys-libs/readline:=
+	virtual/zlib
+"
+
+DEPEND="${RDEPEND}"
+BDEPEND="
+	${PYTHON_DEPS}
+	dev-vcs/git
+	virtual/pkgconfig
+"
+
+src_prepare() {
+	default
+
+	# Fix execute permissions and add shebang for Python scripts
+	local script
+	while IFS= read -r -d '' script; do
+		chmod +x "${script}" || die
+		# Add shebang if missing
+		if ! head -n 1 "${script}" | grep -q '^#!'; then
+			sed -i '1i#!/usr/bin/env python3' "${script}" || die
+		fi
+	done < <(find . -name "*.py" -print0)
+
+}
+
+src_configure() {
+	cat <<-__EOF__ >> Makefile.conf || die
+		PREFIX := ${EPREFIX}/usr
+		STRIP := @echo "skipping strip"
+		CXXFLAGS += ${CXXFLAGS}
+		LINKFLAGS += ${LDFLAGS}
+		PYTHON_EXECUTABLE := ${PYTHON}
+	__EOF__
+
+	default
+}