mirrors/guru
1
0
Fork 0
mirror of https://github.com/gentoo-mirror/guru.git synced 2026-07-19 03:53:22 -04:00
Code Issues Packages Projects Releases Wiki Activity

2024-04-30 12:33:29 UTC

Browse Source
This commit is contained in:
Repository mirror & CI
2024-04-30 12:33:29 +00:00
parent f659180ee8
commit ebf41fc232
15 changed files with 137 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
metadata/md5-cache/sci-electronics/verilator-5.022
View File

@@ -14,4 +14,4 @@ RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.022.tar.gz -> verilator-5.022.tar.gz
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 5f49a16f67f81bdf873e3d1f10b10001 autotools 3af8f60c4bdb23e738db506a630898ee multiprocessing 30ead54fa2e2b5f9cd4e612ffc34d0fe python-utils-r1 a1229a86bd0db058e474a2d7d9191cca python-single-r1 75118e916668a74c660a13b0ecb22562
_md5_=b55a5a2189e12021c56f86a36045b184
_md5_=b717aa6048f47173592ca0b1d0ae1e7c

17
metadata/md5-cache/sci-electronics/verilator-5.024 Normal file
View File

@@ -0,0 +1,17 @@
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake ) sys-devel/gnuconfig >=app-portage/elt-patches-20240116 || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=prepare setup test
DEPEND=python_single_target_python3_10? ( dev-lang/python:3.10 ) python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
HOMEPAGE=https://verilator.org https://github.com/verilator/verilator
INHERIT=autotools python-single-r1
IUSE=debug test python_single_target_python3_10 python_single_target_python3_11 python_single_target_python3_12
KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86
LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=python_single_target_python3_10? ( dev-lang/python:3.10 ) python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) dev-lang/perl sys-libs/zlib
REQUIRED_USE=^^ ( python_single_target_python3_10 python_single_target_python3_11 python_single_target_python3_12 )
RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.024.tar.gz -> verilator-5.024.tar.gz
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 5f49a16f67f81bdf873e3d1f10b10001 autotools 3af8f60c4bdb23e738db506a630898ee multiprocessing 30ead54fa2e2b5f9cd4e612ffc34d0fe python-utils-r1 a1229a86bd0db058e474a2d7d9191cca python-single-r1 75118e916668a74c660a13b0ecb22562
_md5_=b717aa6048f47173592ca0b1d0ae1e7c

2
metadata/md5-cache/sci-electronics/verilator-9999
View File

@@ -13,4 +13,4 @@ REQUIRED_USE=^^ ( python_single_target_python3_10 python_single_target_python3_1
RESTRICT=!test? ( test )
SLOT=0
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 5f49a16f67f81bdf873e3d1f10b10001 autotools 3af8f60c4bdb23e738db506a630898ee multiprocessing 30ead54fa2e2b5f9cd4e612ffc34d0fe python-utils-r1 a1229a86bd0db058e474a2d7d9191cca python-single-r1 75118e916668a74c660a13b0ecb22562 git-r3 fbb2889c81f3a05910c1524db69425c1
_md5_=b55a5a2189e12021c56f86a36045b184
_md5_=b717aa6048f47173592ca0b1d0ae1e7c

12
metadata/md5-cache/sci-electronics/yosys-0.32 Normal file
View File

@@ -0,0 +1,12 @@
BDEPEND=dev-vcs/git
DEFINED_PHASES=install prepare
DEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=http://www.clifford.at/yosys/
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/archive/yosys-0.32.tar.gz https://github.com/YosysHQ/abc/archive/bb64142b07794ee685494564471e67365a093710.tar.gz -> abc-bb64142b07794ee685494564471e67365a093710.tar.gz
_md5_=9c8a43f1fbffe94d80e8488434172d6a

12
metadata/md5-cache/sci-electronics/yosys-0.40 Normal file
View File

@@ -0,0 +1,12 @@
BDEPEND=dev-vcs/git
DEFINED_PHASES=install prepare
DEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=http://www.clifford.at/yosys/
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/archive/yosys-0.40.tar.gz https://github.com/YosysHQ/abc/archive/0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz -> abc-0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz
_md5_=76693ca4ccaf7eeb45967748d91725b5