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2020-06-13 14:35:06 UTC

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2020-06-13 14:35:06 +00:00
parent 849a8675b2
commit c3245d4994
3 changed files with 15 additions and 2 deletions
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metadata/md5-cache/sci-electronics/verilator-4.036 Normal file
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BDEPEND=sys-devel/bison sys-devel/flex >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4
DEFINED_PHASES=prepare
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=7
HOMEPAGE=https://verilator.org https://github.com/verilator/verilator
KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86
LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v4.036.tar.gz -> verilator-4.036.tar.gz
_eclasses_=autotools 7d999b62b8749fad43fff00620cedf47 libtool f143db5a74ccd9ca28c1234deffede96 multilib 0914eab919f4f11dd9e0407b92af4726 toolchain-funcs d3e75048a89c0445838d2f44e5c65d97
_md5_=daf1fe3e48c8ad5d5fe1f017b86b6c87