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sci-electronics/circt: new package, add 1.14.0
Signed-off-by: Huang Rui <vowstar@gmail.com>
This commit is contained in:
Huang Rui
2
sci-electronics/circt/Manifest
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2
sci-electronics/circt/Manifest
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DIST circt-1.14.0.tar.gz 2152570 BLAKE2B 3901c0d146a4410cc2ee5a0556ce54decea4fb1998b83a2999ec97493efcdefbb2bb0c33b5ee127c9627568bdd92669bf1c064930abf6954aa33cbb382fea006 SHA512 1d2b2696c7ce42cf90a9209f2b0d04862681645cfe733e0dd2f6c48754a9fa035f2d5033b2c0278841edaaee9a72802a00226f210a032e81b79d4d3df5bcf7cf
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DIST llvm-project-fe0f72d5c55a9b95c5564089e946e8f08112e995.tar.gz 166019098 BLAKE2B c3613d5465522249597fe8a882cd4cdd2f8b4030a9fee73c47643f0e64ea0b97a212f9e4637e5a096e30e679460dac039b0c244daf4b0bd04c4da42efb4744d0 SHA512 bc71f42c8af87559fbc384a6cf473b5bdb42a04e698e7e44c94d9ea27f763d7f0bd4dea63e0eef9d29cdfb2ad203b14eeb6431bba336583cfb0ce19f12a40a72
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116
sci-electronics/circt/circt-1.14.0.ebuild
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sci-electronics/circt/circt-1.14.0.ebuild
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# Copyright 1999-2022 Gentoo Authors
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# Distributed under the terms of the GNU General Public License v2
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EAPI="8"
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MY_PV="$(ver_cut 1)/$(ver_cut 2)/$(ver_cut 3)"
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MY_LLVM_PV="fe0f72d5c55a9b95c5564089e946e8f08112e995"
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CMAKE_BUILD_TYPE="Release"
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CMAKE_MAKEFILE_GENERATOR="ninja"
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PYTHON_COMPAT=( python3_{8..11} )
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inherit cmake python-r1
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DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
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HOMEPAGE="
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https://circt.llvm.org
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https://github.com/llvm/circt
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"
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if [[ "${PV}" == "9999" ]] ; then
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inherit git-r3
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EGIT_REPO_URI="https://github.com/llvm/${PN}.git"
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EGIT_SUBMODULES=( '*' )
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else
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SRC_URI="
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https://github.com/llvm/circt/archive/refs/tags/sifive/${MY_PV}.tar.gz -> ${P}.tar.gz
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https://github.com/llvm/llvm-project/archive/${MY_LLVM_PV}.tar.gz -> llvm-project-${MY_LLVM_PV}.tar.gz
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"
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KEYWORDS="~amd64 ~arm64 ~riscv ~x86"
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S_CIRCT="${WORKDIR}/${PN}-sifive-$(ver_cut 1)-$(ver_cut 2)-$(ver_cut 3)"
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S_LLVM="${WORKDIR}/llvm-project-${MY_LLVM_PV}"
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S="${S_LLVM}/llvm"
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fi
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LICENSE="Apache-2.0-with-LLVM-exceptions UoI-NCSA BSD public-domain rc"
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SLOT="0"
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IUSE="test"
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REQUIRED_USE=" ${PYTHON_REQUIRED_USE} "
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RESTRICT="!test? ( test )"
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RDEPEND="
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${PYTHON_DEPS}
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test? (
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dev-python/psutil[${PYTHON_USEDEP}]
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sci-electronics/verilator
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)
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sys-libs/ncurses:0=
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"
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DEPEND="
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${RDEPEND}
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"
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BDEPEND="
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dev-util/ninja
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virtual/pkgconfig
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"
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DOCS=(
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"${S_LLVM}/llvm/llvm-LICENSE.TXT"
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"${S_LLVM}/mlir/mlir-LICENSE.TXT"
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"${S_CIRCT}/circt-LICENSE"
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)
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src_configure() {
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python_setup
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local mycmakeargs=(
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-D Python3_EXECUTABLE="${PYTHON}" \
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-D CMAKE_INSTALL_PREFIX=/usr \
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-D LLVM_BINUTILS_INCDIR=/usr/include \
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-D LLVM_ENABLE_PROJECTS=mlir \
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-D BUILD_SHARED_LIBS=OFF \
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-D LLVM_STATIC_LINK_CXX_STDLIB=ON \
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-D LLVM_ENABLE_ASSERTIONS=ON \
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-D LLVM_BUILD_EXAMPLES=OFF \
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-D LLVM_ENABLE_BINDINGS=OFF \
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-D LLVM_ENABLE_OCAMLDOC=OFF \
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-D LLVM_OPTIMIZED_TABLEGEN=ON \
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-D LLVM_EXTERNAL_PROJECTS=circt \
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-D LLVM_EXTERNAL_CIRCT_SOURCE_DIR="${S_CIRCT}" \
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-D LLVM_BUILD_TOOLS=ON
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)
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cmake_src_configure
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}
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src_test() {
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pushd "${BUILD_DIR}" || die
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eninja check-mlir
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eninja check-circt
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eninja check-circt-integration
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popd || die
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}
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src_install() {
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mv "${S_LLVM}/llvm/LICENSE.TXT" "${S_LLVM}/llvm/llvm-LICENSE.TXT" || die
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mv "${S_LLVM}/mlir/LICENSE.TXT" "${S_LLVM}/mlir/mlir-LICENSE.TXT" || die
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mv "${S_CIRCT}/LICENSE" "${S_CIRCT}/circt-LICENSE" || die
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einstalldocs
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exeinto /usr/bin
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doexe "${BUILD_DIR}"/bin/circt-capi-ir-test
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doexe "${BUILD_DIR}"/bin/circt-lsp-server
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doexe "${BUILD_DIR}"/bin/circt-opt
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doexe "${BUILD_DIR}"/bin/circt-reduce
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doexe "${BUILD_DIR}"/bin/circt-rtl-sim.py
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doexe "${BUILD_DIR}"/bin/circt-translate
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doexe "${BUILD_DIR}"/bin/esi_cosim.py
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doexe "${BUILD_DIR}"/bin/esi-cosim-runner.py
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doexe "${BUILD_DIR}"/bin/esi-tester
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doexe "${BUILD_DIR}"/bin/firtool
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doexe "${BUILD_DIR}"/bin/handshake-runner
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doexe "${BUILD_DIR}"/bin/llhd-sim
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doexe "${BUILD_DIR}"/bin/py-split-input-file.py
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# llhd-sim not static linked
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dolib.so "${BUILD_DIR}"/lib/libcirct-llhd-signals-runtime-wrappers.so
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}
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18
sci-electronics/circt/metadata.xml
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18
sci-electronics/circt/metadata.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE pkgmetadata SYSTEM "https://www.gentoo.org/dtd/metadata.dtd">
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<pkgmetadata>
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<maintainer type="person">
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<email>vowstar@gmail.com</email>
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<name>Huang Rui</name>
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</maintainer>
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<upstream>
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<remote-id type="github">verilator/verilator</remote-id>
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</upstream>
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<longdescription lang="en">
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Verilator, the fastest free Verilog HDL simulator.
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Accepts synthesizable Verilog or SystemVerilog
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Performs lint code-quality checks
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Compiles into multithreaded C++, SystemC, or (soon) C++-under-Python
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Creates XML to front-end your own tools
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</longdescription>
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</pkgmetadata>
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