sci-electronics/verilator: fix compile problem

Add patch file to live ebuild.

Package-Manager: Portage-2.3.99, Repoman-2.3.22
Signed-off-by: Huang Rui <vowstar@gmail.com>

sci-electronics/verilator/verilator-9999.ebuild

@@ -6,13 +6,16 @@ EAPI="7"
 inherit autotools
 
 DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
-HOMEPAGE="https://www.veripool.org/wiki/verilator"
+HOMEPAGE="
+	https://verilator.org
+	https://github.com/verilator/verilator
+"
 
 if [[ "${PV}" == "9999" ]] ; then
 	inherit git-r3
-	EGIT_REPO_URI="https://git.veripool.org/git/${PN}"
+	EGIT_REPO_URI="https://github.com/${PN}/${PN}.git"
 else
-	SRC_URI="http://www.veripool.org/ftp/${P}.tgz -> ${P}.tar.gz"
+	SRC_URI="https://github.com/${PN}/${PN}/archive/v${PV}.tar.gz -> ${P}.tar.gz"
 	KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86"
 fi
 
@@ -33,6 +36,11 @@ BDEPEND="
 	sys-devel/flex
 "
 
+PATCHES=(
+	# https://github.com/verilator/verilator/issues/2320
+	"${FILESDIR}"/${PN}-4.034-fix-bison.patch
+)
+
 src_prepare() {
 	default
 	eautoconf --force