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2024-10-11 10:03:26 UTC

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2024-10-11 10:03:26 +00:00
parent f7962cb648
commit ab30c97d7f
35 changed files with 237 additions and 186 deletions
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6
metadata/md5-cache/sci-electronics/verilator-5.026 → metadata/md5-cache/sci-electronics/verilator-5.026-r1
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@@ -1,5 +1,5 @@
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake ) >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=prepare setup test
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=configure prepare setup test
DEPEND=python_single_target_python3_10? ( dev-lang/python:3.10 ) python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
@@ -14,4 +14,4 @@ RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.026.tar.gz -> verilator-5.026.tar.gz
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs d3d42b22a610ce81c267b644bcec9b87 multilib b2a329026f2e404e9e371097dda47f96 libtool 6b28392a775f807c8be5fc7ec9a605b9 autotools 7d91cc798a8afd8f4e0c6e9587296ebe multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 c356a67b8e93889de6efff7d50599102 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_md5_=74d2ca7fde9f3ee237a277f4e797a025
_md5_=d5b86c030bf739f6013b755738b91174

6
metadata/md5-cache/sci-electronics/verilator-5.028 → metadata/md5-cache/sci-electronics/verilator-5.028-r1
View File

@@ -1,5 +1,5 @@
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake ) >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=prepare setup test
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=configure prepare setup test
DEPEND=python_single_target_python3_10? ( dev-lang/python:3.10 ) python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
@@ -14,4 +14,4 @@ RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.028.tar.gz -> verilator-5.028.tar.gz
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs d3d42b22a610ce81c267b644bcec9b87 multilib b2a329026f2e404e9e371097dda47f96 libtool 6b28392a775f807c8be5fc7ec9a605b9 autotools 7d91cc798a8afd8f4e0c6e9587296ebe multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 c356a67b8e93889de6efff7d50599102 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_md5_=74d2ca7fde9f3ee237a277f4e797a025
_md5_=d5b86c030bf739f6013b755738b91174

6
metadata/md5-cache/sci-electronics/verilator-9999
View File

@@ -1,5 +1,5 @@
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake ) >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3 >=dev-vcs/git-1.8.2.1[curl]
DEFINED_PHASES=prepare setup test unpack
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3 >=dev-vcs/git-1.8.2.1[curl]
DEFINED_PHASES=configure prepare setup test unpack
DEPEND=python_single_target_python3_10? ( dev-lang/python:3.10 ) python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
@@ -13,4 +13,4 @@ REQUIRED_USE=^^ ( python_single_target_python3_10 python_single_target_python3_1
RESTRICT=!test? ( test )
SLOT=0
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs d3d42b22a610ce81c267b644bcec9b87 multilib b2a329026f2e404e9e371097dda47f96 libtool 6b28392a775f807c8be5fc7ec9a605b9 autotools 7d91cc798a8afd8f4e0c6e9587296ebe multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 c356a67b8e93889de6efff7d50599102 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57 git-r3 875eb471682d3e1f18da124be97dcc81
_md5_=74d2ca7fde9f3ee237a277f4e797a025
_md5_=d5b86c030bf739f6013b755738b91174