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2026-01-17 07:16:10 UTC

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2026-01-17 07:16:10 +00:00
parent 1b9b656911
commit a2eebf9528
38 changed files with 301 additions and 131 deletions
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2
metadata/md5-cache/sci-electronics/sby-0.60 → metadata/md5-cache/sci-electronics/sby-0.61
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@@ -10,6 +10,6 @@ LICENSE=ISC
RDEPEND=python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) python_single_target_python3_14? ( dev-lang/python:3.14 ) python_single_target_python3_11? ( dev-python/click[python_targets_python3_11(-)] ) python_single_target_python3_12? ( dev-python/click[python_targets_python3_12(-)] ) python_single_target_python3_13? ( dev-python/click[python_targets_python3_13(-)] ) python_single_target_python3_14? ( dev-python/click[python_targets_python3_14(-)] ) sci-electronics/yosys sci-mathematics/z3 yices2? ( sci-mathematics/yices2 )
REQUIRED_USE=^^ ( python_single_target_python3_11 python_single_target_python3_12 python_single_target_python3_13 python_single_target_python3_14 )
SLOT=0
SRC_URI=https://github.com/YosysHQ/sby/archive/v0.60.tar.gz -> sby-0.60.tar.gz
SRC_URI=https://github.com/YosysHQ/sby/archive/v0.61.tar.gz -> sby-0.61.tar.gz
_eclasses_=multiprocessing 1e32df7deee68372153dca65f4a7c21f toolchain-funcs 30214924c0c3b92ec7dbf24fc70d60d3 python-utils-r1 dbb8c4d794033ad7e7221eaf567a6c90 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_md5_=69cca7a17786029ae22f9a1754d8b4f8

12
metadata/md5-cache/sci-electronics/yosys-0.60
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@@ -1,12 +0,0 @@
BDEPEND=dev-vcs/git
DEFINED_PHASES=configure
DEPEND=dev-libs/boost media-gfx/xdot llvm-core/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=https://yosyshq.net/yosys/
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost media-gfx/xdot llvm-core/clang
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/releases/download/v0.60/yosys.tar.gz -> yosys-0.60.tar.gz
_md5_=3885297d9da518b7b6d3b29c0e33826a

16
metadata/md5-cache/sci-electronics/yosys-0.61-r1 Normal file
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@@ -0,0 +1,16 @@
BDEPEND=|| ( dev-lang/python:3.14 dev-lang/python:3.13 dev-lang/python:3.12 dev-lang/python:3.11 ) dev-vcs/git virtual/pkgconfig
DEFINED_PHASES=configure prepare setup
DEPEND=dev-libs/boost:= dev-libs/libffi:= dev-lang/tcl:= llvm_slot_18? ( llvm-core/clang:18= ) llvm_slot_19? ( llvm-core/clang:19= ) llvm_slot_20? ( llvm-core/clang:20= ) llvm_slot_21? ( llvm-core/clang:21= ) media-gfx/xdot sys-libs/ncurses:= sys-libs/readline:= virtual/zlib
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=https://yosyshq.net/yosys/
INHERIT=python-any-r1 llvm-r2
IUSE=+llvm_slot_21 llvm_slot_18 llvm_slot_19 llvm_slot_20
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost:= dev-libs/libffi:= dev-lang/tcl:= llvm_slot_18? ( llvm-core/clang:18= ) llvm_slot_19? ( llvm-core/clang:19= ) llvm_slot_20? ( llvm-core/clang:20= ) llvm_slot_21? ( llvm-core/clang:21= ) media-gfx/xdot sys-libs/ncurses:= sys-libs/readline:= virtual/zlib
REQUIRED_USE=^^ ( llvm_slot_18 llvm_slot_19 llvm_slot_20 llvm_slot_21 )
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/releases/download/v0.61/yosys.tar.gz -> yosys-0.61.tar.gz
_eclasses_=multiprocessing 1e32df7deee68372153dca65f4a7c21f toolchain-funcs 30214924c0c3b92ec7dbf24fc70d60d3 python-utils-r1 dbb8c4d794033ad7e7221eaf567a6c90 python-any-r1 891415dfe39ad9b41b461f2b86354af0 llvm-utils 64536677f4b4365e25e9b739163bed58 multilib 404b65bd5212cff83b3935c685419d08 llvm-r2 d6b14d3bbccc5ab5b4182c606245dbd3
_md5_=4d3b5ab5e4db3b4928ee2f38bf3aa92e