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2025-05-28 03:54:41 UTC

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2025-05-28 03:54:41 +00:00
parent aa7da55372
commit 9d45a943c5
124 changed files with 247 additions and 247 deletions
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4
metadata/md5-cache/sci-electronics/verilator-5.026-r1
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@@ -1,4 +1,4 @@
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) sys-devel/gnuconfig >=app-portage/elt-patches-20250306 || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 ) >=dev-build/libtool-2.4.7-r3
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) sys-devel/gnuconfig >=app-portage/elt-patches-20250306 || ( >=dev-build/automake-1.18:1.18 >=dev-build/automake-1.17-r1:1.17 ) || ( >=dev-build/autoconf-2.72-r1:2.72 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=configure prepare setup test
DEPEND=python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
@@ -13,5 +13,5 @@ REQUIRED_USE=^^ ( python_single_target_python3_11 python_single_target_python3_1
RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.026.tar.gz -> verilator-5.026.tar.gz
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs f9d71a6efe9d083aec750dd13968e169 libtool c81bd096be5f4c82f4e8f156ef112402 autotools 35f9bf6198bb538e28dcdea5fda274f2 multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 e6fe2c451b7e577e827165580e5bdd64 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs f9d71a6efe9d083aec750dd13968e169 libtool c81bd096be5f4c82f4e8f156ef112402 autotools 216128ca9bbff45fbea22427005310c7 multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 e6fe2c451b7e577e827165580e5bdd64 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_md5_=80698769d863a414767b4397c1dfc066

4
metadata/md5-cache/sci-electronics/verilator-5.028-r1
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@@ -1,4 +1,4 @@
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) sys-devel/gnuconfig >=app-portage/elt-patches-20250306 || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 ) >=dev-build/libtool-2.4.7-r3
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) sys-devel/gnuconfig >=app-portage/elt-patches-20250306 || ( >=dev-build/automake-1.18:1.18 >=dev-build/automake-1.17-r1:1.17 ) || ( >=dev-build/autoconf-2.72-r1:2.72 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=configure prepare setup test
DEPEND=python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
@@ -13,5 +13,5 @@ REQUIRED_USE=^^ ( python_single_target_python3_11 python_single_target_python3_1
RESTRICT=!test? ( test )
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.028.tar.gz -> verilator-5.028.tar.gz
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs f9d71a6efe9d083aec750dd13968e169 libtool c81bd096be5f4c82f4e8f156ef112402 autotools 35f9bf6198bb538e28dcdea5fda274f2 multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 e6fe2c451b7e577e827165580e5bdd64 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs f9d71a6efe9d083aec750dd13968e169 libtool c81bd096be5f4c82f4e8f156ef112402 autotools 216128ca9bbff45fbea22427005310c7 multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 e6fe2c451b7e577e827165580e5bdd64 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57
_md5_=80698769d863a414767b4397c1dfc066

4
metadata/md5-cache/sci-electronics/verilator-9999
View File

@@ -1,4 +1,4 @@
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) sys-devel/gnuconfig >=app-portage/elt-patches-20250306 || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 ) >=dev-build/libtool-2.4.7-r3 >=dev-vcs/git-1.8.2.1[curl]
BDEPEND=sys-devel/bison sys-devel/flex test? ( dev-build/cmake dev-debug/gdb ) sys-devel/gnuconfig >=app-portage/elt-patches-20250306 || ( >=dev-build/automake-1.18:1.18 >=dev-build/automake-1.17-r1:1.17 ) || ( >=dev-build/autoconf-2.72-r1:2.72 ) >=dev-build/libtool-2.4.7-r3 >=dev-vcs/git-1.8.2.1[curl]
DEFINED_PHASES=configure prepare setup test unpack
DEPEND=python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_target_python3_12? ( dev-lang/python:3.12 ) python_single_target_python3_13? ( dev-lang/python:3.13 ) dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
@@ -12,5 +12,5 @@ RDEPEND=python_single_target_python3_11? ( dev-lang/python:3.11 ) python_single_
REQUIRED_USE=^^ ( python_single_target_python3_11 python_single_target_python3_12 python_single_target_python3_13 )
RESTRICT=!test? ( test )
SLOT=0
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs f9d71a6efe9d083aec750dd13968e169 libtool c81bd096be5f4c82f4e8f156ef112402 autotools 35f9bf6198bb538e28dcdea5fda274f2 multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 e6fe2c451b7e577e827165580e5bdd64 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57 git-r3 875eb471682d3e1f18da124be97dcc81
_eclasses_=gnuconfig ddeb9f8caff1b5f71a09c75b7534df79 toolchain-funcs f9d71a6efe9d083aec750dd13968e169 libtool c81bd096be5f4c82f4e8f156ef112402 autotools 216128ca9bbff45fbea22427005310c7 multiprocessing 1e32df7deee68372153dca65f4a7c21f python-utils-r1 e6fe2c451b7e577e827165580e5bdd64 python-single-r1 47d8ac9be330c9366112b78fd4f8ce57 git-r3 875eb471682d3e1f18da124be97dcc81
_md5_=80698769d863a414767b4397c1dfc066