sci-electronics/verible: new package, add 0.0.2135

Signed-off-by: Huang Rui <vowstar@gmail.com>

sci-electronics/verible/metadata.xml

@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
+<pkgmetadata>
+	<maintainer type="person">
+		<email>vowstar@gmail.com</email>
+		<name>Huang Rui</name>
+	</maintainer>
+	<upstream>
+		<remote-id type="github">chipsalliance/verible</remote-id>
+	</upstream>
+	<longdescription lang="en">
+	Verible is a suite of SystemVerilog developer tools, including a parser,
+	style-linter, and formatter.
+	The Verible project's main mission is to parse SystemVerilog
+	(IEEE 1800-2017) (as standardized in the SV-LRM) for a wide variety of
+	applications, including developer tools.
+	It was born out of a need to parse un-preprocessed source files, which is
+	suitable for single-file applications like style-linting and formatting.
+	In doing so, it can be adapted to parse preprocessed source files, which is
+	what real compilers and toolchains require.
+	The spirit of the project is that no-one should ever have to develop a
+	SystemVerilog parser for their own application, because developing a
+	standard-compliant parser is an enormous task due to the syntactic
+	complexity of the language. Verible's parser is also regularly tested
+	against an ever-growing suite of (tool-independent) language compliance
+	tests at https://symbiflow.github.io/sv-tests/.
+	A lesser (but notable) objective is that the language-agnostic components
+	of Verible be usable for rapidly developing language support tools for
+	other languages.
+	</longdescription>
+</pkgmetadata>