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2024-01-15 16:18:31 UTC

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2024-01-15 16:18:32 +00:00
parent 5d52078267
commit 48e95ac7fa
238 changed files with 475 additions and 475 deletions
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4
metadata/md5-cache/sci-electronics/verilator-4.106
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@@ -1,4 +1,4 @@
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7
DEFINED_PHASES=prepare
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
@@ -10,5 +10,5 @@ LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v4.106.tar.gz -> verilator-4.106.tar.gz
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools 5f729b9cb10d5eda573cd604c93c6dc5
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools e4cf390b19033d5ca443765bc8537b81
_md5_=af5b9fd6095d78410d1362081e92d9bb

4
metadata/md5-cache/sci-electronics/verilator-5.014
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@@ -1,4 +1,4 @@
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7
DEFINED_PHASES=prepare
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
@@ -10,5 +10,5 @@ LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.014.tar.gz -> verilator-5.014.tar.gz
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools 5f729b9cb10d5eda573cd604c93c6dc5
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools e4cf390b19033d5ca443765bc8537b81
_md5_=af5b9fd6095d78410d1362081e92d9bb

4
metadata/md5-cache/sci-electronics/verilator-5.018
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@@ -1,4 +1,4 @@
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7
DEFINED_PHASES=prepare
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
@@ -10,5 +10,5 @@ LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.018.tar.gz -> verilator-5.018.tar.gz
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools 5f729b9cb10d5eda573cd604c93c6dc5
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools e4cf390b19033d5ca443765bc8537b81
_md5_=af5b9fd6095d78410d1362081e92d9bb

4
metadata/md5-cache/sci-electronics/verilator-9999
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@@ -1,4 +1,4 @@
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7 >=dev-vcs/git-1.8.2.1[curl]
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7 >=dev-vcs/git-1.8.2.1[curl]
DEFINED_PHASES=prepare unpack
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
@@ -9,5 +9,5 @@ LICENSE=|| ( Artistic-2 LGPL-3 )
PROPERTIES=live
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools 5f729b9cb10d5eda573cd604c93c6dc5 git-r3 86fa1f157b70b9d2ff340c4633b1cf4b
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 9d3a9a889a6fa62ae794f817c156491b autotools e4cf390b19033d5ca443765bc8537b81 git-r3 86fa1f157b70b9d2ff340c4633b1cf4b
_md5_=af5b9fd6095d78410d1362081e92d9bb