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2022-02-20 09:06:46 UTC

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2022-02-20 09:06:46 +00:00
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commit 3bc04610ce
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metadata/md5-cache/sci-electronics/verilator-4.218 Normal file
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BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.4:1.16 ) >=sys-devel/autoconf-2.71 >=sys-devel/libtool-2.4
DEFINED_PHASES=prepare
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
HOMEPAGE=https://verilator.org https://github.com/verilator/verilator
INHERIT=autotools
KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86
LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v4.218.tar.gz -> verilator-4.218.tar.gz
_eclasses_=gnuconfig 262062cef0ba4f22b397193da514a350 toolchain-funcs badd6e329e1f3e6bee99b35bf8763ce8 multilib de4beb52bfa93c4c5d96792a6b5e1784 libtool 241a8f577b9781a42a7421e53448a44e autotools 6cc26735fa9dd59e8c62880beda05b6e
_md5_=0fdb3bcdfcdd5d1d8b7d4780dee28459