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2024-05-07 04:05:25 UTC

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2024-05-07 04:05:25 +00:00
parent b1a5d88592
commit 1fd9dd3f75
11 changed files with 59 additions and 45 deletions
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4
metadata/md5-cache/sci-electronics/yosys-0.40 → metadata/md5-cache/sci-electronics/yosys-0.40-r1
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@@ -1,5 +1,5 @@
BDEPEND=dev-vcs/git
DEFINED_PHASES=install prepare
DEFINED_PHASES=configure prepare
DEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
@@ -9,4 +9,4 @@ LICENSE=ISC
RDEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/archive/yosys-0.40.tar.gz https://github.com/YosysHQ/abc/archive/0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz -> abc-0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz
_md5_=76693ca4ccaf7eeb45967748d91725b5
_md5_=953a8c4d2392f5733c4b79e917a960d4