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sci-electronics/verilator: improve ebuilds

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Make it fit the standards of gentoo GLEPs.

Package-Manager: Portage-2.3.99, Repoman-2.3.22
Signed-off-by: Huang Rui <vowstar@gmail.com>
This commit is contained in:
Huang Rui
2020-04-27 14:47:54 +08:00
parent 52b39a04b4
commit 1e837779e6
1 changed files with 2 additions and 2 deletions
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4
sci-electronics/verilator/verilator-4.032.ebuild
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@@ -1,14 +1,14 @@
# Copyright 1999-2020 Gentoo Authors
# Distributed under the terms of the GNU General Public License v2
EAPI=7
EAPI="7"
inherit autotools
DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
HOMEPAGE="https://www.veripool.org/wiki/verilator"
if [[ ${PV} == "9999" ]] ; then
if [[ "${PV}" == "9999" ]] ; then
inherit git-r3
EGIT_REPO_URI="https://git.veripool.org/git/${PN}"
else