sci-electronics/verilator: drop 4.106

Closes: https://bugs.gentoo.org/885691
Closes: https://bugs.gentoo.org/885735
Signed-off-by: Huang Rui <vowstar@gmail.com>
This commit is contained in:
Huang Rui
2024-03-18 21:17:03 +08:00
parent b3bf1ae0a3
commit 12ac6bf158
2 changed files with 0 additions and 47 deletions

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DIST verilator-4.106.tar.gz 2191982 BLAKE2B 9dbd0dad390b4a009a062a8405dc01a317fed68a2f0becd4bf088c566f2457a4cda04a4c276cf31cdbaa0efa6e64f5618b9439221f8cf4bb469f20f1de1af397 SHA512 b1840b294b22c0d4cf17a0a154e73a631c62b30055f324dca98839ab85e2a524f9e3b6e981b192b941c1dd9837f326ae38cc3fcf686c3f8731d376dc89dd46fe
DIST verilator-5.022.tar.gz 3761782 BLAKE2B 49713ce89f101eb6f6165ee316fc018936ccb21fd6ceccce343684ff3cca10285f851172549843078801e69828f0069877ec68a8ac39a1fbce4a2426d3e4b44d SHA512 5b919ed5d4cf863434f10f39bbb3a5155d63f79765f5f1d5ae543023b0e350e0996507d250fbfb2e5129bbdf9a51cc5fd0b7154962747c89435648897525bc84

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# Copyright 1999-2023 Gentoo Authors
# Distributed under the terms of the GNU General Public License v2
EAPI="8"
inherit autotools
DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
HOMEPAGE="
https://verilator.org
https://github.com/verilator/verilator
"
if [[ "${PV}" == "9999" ]] ; then
inherit git-r3
EGIT_REPO_URI="https://github.com/${PN}/${PN}.git"
else
SRC_URI="https://github.com/${PN}/${PN}/archive/v${PV}.tar.gz -> ${P}.tar.gz"
KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86"
fi
LICENSE="|| ( Artistic-2 LGPL-3 )"
SLOT="0"
RDEPEND="
dev-lang/perl
sys-libs/zlib
"
DEPEND="
${RDEPEND}
"
BDEPEND="
sys-devel/bison
sys-devel/flex
"
src_prepare() {
default
if [[ ! "${PV}" == "9999" ]] ; then
# https://github.com/verilator/verilator/issues/3352
sed -i "s/UNKNOWN_REV/(Gentoo ${PVR})/g" "${S}"/src/config_rev || die
fi
eautoconf --force
}