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2024-12-12 13:18:22 UTC

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2024-12-12 13:18:22 +00:00
parent 5943503a7e
commit 0e5174954c
83 changed files with 327 additions and 196 deletions
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6
metadata/md5-cache/sci-electronics/yosys-0.40-r1
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@@ -1,12 +1,12 @@
BDEPEND=dev-vcs/git
DEFINED_PHASES=configure prepare
DEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
DEPEND=dev-libs/boost media-gfx/xdot llvm-core/clang
DESCRIPTION=framework for Verilog RTL synthesis
EAPI=8
HOMEPAGE=http://www.clifford.at/yosys/
KEYWORDS=~amd64
LICENSE=ISC
RDEPEND=dev-libs/boost media-gfx/xdot sys-devel/clang
RDEPEND=dev-libs/boost media-gfx/xdot llvm-core/clang
SLOT=0
SRC_URI=https://github.com/YosysHQ/yosys/archive/yosys-0.40.tar.gz https://github.com/YosysHQ/abc/archive/0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz -> abc-0cd90d0d2c5338277d832a1d890bed286486bcf5.tar.gz
_md5_=d26f8a90a1fc2acbbc8b82743637f043
_md5_=1e442aa7ea692ce9bfd5acdde4887a3f