diff --git a/sci-electronics/circt/circt-1.37.0.ebuild b/sci-electronics/circt/circt-1.37.0.ebuild
index 0b1a877e51..e3254ff3cb 100644
--- a/sci-electronics/circt/circt-1.37.0.ebuild
+++ b/sci-electronics/circt/circt-1.37.0.ebuild
@@ -6,7 +6,7 @@ EAPI="8"
 MY_PV="${PV//./\/}"
 MY_LLVM_PV="d978730d8e2c10c76867b83bec2f1143d895ee7d"
 CMAKE_BUILD_TYPE="Release"
-PYTHON_COMPAT=( python3_{11..12} )
+PYTHON_COMPAT=( python3_{11..13} )
 inherit cmake python-r1
 
 DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
diff --git a/sci-electronics/circt/circt-1.76.0.ebuild b/sci-electronics/circt/circt-1.76.0.ebuild
index 55b05c8d13..ad2727dc82 100644
--- a/sci-electronics/circt/circt-1.76.0.ebuild
+++ b/sci-electronics/circt/circt-1.76.0.ebuild
@@ -6,7 +6,7 @@ EAPI="8"
 MY_PV="${PV//./\/}"
 MY_LLVM_PV="6595e7fa1b5588f860aa057aac47c43623169584"
 CMAKE_BUILD_TYPE="Release"
-PYTHON_COMPAT=( python3_{11..12} )
+PYTHON_COMPAT=( python3_{11..13} )
 inherit cmake python-r1
 
 DESCRIPTION="The fast free Verilog/SystemVerilog simulator"