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2023-01-31 11:17:02 UTC

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2023-01-31 11:17:03 +00:00
parent 6ec4dda0d5
commit 0c537dc5dd
11 changed files with 40 additions and 24 deletions
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4
metadata/md5-cache/sci-electronics/verilator-4.228 → metadata/md5-cache/sci-electronics/verilator-4.106
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@@ -9,6 +9,6 @@ KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s
LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v4.228.tar.gz -> verilator-4.228.tar.gz
SRC_URI=https://github.com/verilator/verilator/archive/v4.106.tar.gz -> verilator-4.106.tar.gz
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs 9a610728b9bcca1919234cceb35a1027 multilib 5ca4e49abed8e3a2f7b56920eadee157 libtool 241a8f577b9781a42a7421e53448a44e autotools 6dcd6b6a486e79928e1243ff9ba41fcc
_md5_=0fdb3bcdfcdd5d1d8b7d4780dee28459
_md5_=4d5f8b501ad830d9b933140704ce6640

14
metadata/md5-cache/sci-electronics/verilator-5.006 Normal file
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@@ -0,0 +1,14 @@
BDEPEND=sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) >=sys-devel/autoconf-2.71-r5 >=sys-devel/libtool-2.4.7
DEFINED_PHASES=prepare
DEPEND=dev-lang/perl sys-libs/zlib
DESCRIPTION=The fast free Verilog/SystemVerilog simulator
EAPI=8
HOMEPAGE=https://verilator.org https://github.com/verilator/verilator
INHERIT=autotools
KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86
LICENSE=|| ( Artistic-2 LGPL-3 )
RDEPEND=dev-lang/perl sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/verilator/verilator/archive/v5.006.tar.gz -> verilator-5.006.tar.gz
_eclasses_=gnuconfig b6b3e92f8b8c996400074b5f61a59256 toolchain-funcs 9a610728b9bcca1919234cceb35a1027 multilib 5ca4e49abed8e3a2f7b56920eadee157 libtool 241a8f577b9781a42a7421e53448a44e autotools 6dcd6b6a486e79928e1243ff9ba41fcc
_md5_=4d5f8b501ad830d9b933140704ce6640