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sci-electronics/verilator: new package 4.026

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The fast free Verilog/SystemVerilog simulator

Closes: https://bugs.gentoo.org/354957
Package-Manager: Portage-2.3.89, Repoman-2.3.20
Signed-off-by: Huang Rui <vowstar@gmail.com>
This commit is contained in:
Huang Rui
2020-02-23 14:51:23 +08:00
parent f1d35f4555
commit 03fda63eac
3 changed files with 59 additions and 0 deletions
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sci-electronics/verilator/metadata.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
<pkgmetadata>
<maintainer type="person">
<email>vowstar@gmail.com</email>
<name>Huang Rui</name>
</maintainer>
<maintainer type="project">
<email>proxy-maint@gentoo.org</email>
<name>Proxy Maintainers</name>
</maintainer>
<longdescription>
Verilator, the fastest free Verilog HDL simulator.
Accepts synthesizable Verilog or SystemVerilog
Performs lint code-quality checks
Compiles into multithreaded C++, SystemC, or (soon) C++-under-Python
Creates XML to front-end your own tools
</longdescription>
</pkgmetadata>