sci-electronics/verilator: new package 4.026

The fast free Verilog/SystemVerilog simulator

Closes: https://bugs.gentoo.org/354957
Package-Manager: Portage-2.3.89, Repoman-2.3.20
Signed-off-by: Huang Rui <vowstar@gmail.com>
This commit is contained in:
Huang Rui
2020-02-23 14:51:23 +08:00
parent f1d35f4555
commit 03fda63eac
3 changed files with 59 additions and 0 deletions

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DIST verilator-4.026.tar.gz 2404465 BLAKE2B a861c16b706a26bb0d9f879a6ac129eca29cfd36c47d044ba8297ce2f4bfbc3d6a8f68f652a0b7db0542373416e975b2266bbf1ea11b0f949c12c1c5f6706b05 SHA512 cc91c44da39b5b0256adf1d43acad22d07bcdc56636336673916a7b01d39c5fc06603b87a9d9e214497a793d1e9ff198593f915f676c99a32f0853f4b74d0527

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
<pkgmetadata>
<maintainer type="person">
<email>vowstar@gmail.com</email>
<name>Huang Rui</name>
</maintainer>
<maintainer type="project">
<email>proxy-maint@gentoo.org</email>
<name>Proxy Maintainers</name>
</maintainer>
<longdescription>
Verilator, the fastest free Verilog HDL simulator.
Accepts synthesizable Verilog or SystemVerilog
Performs lint code-quality checks
Compiles into multithreaded C++, SystemC, or (soon) C++-under-Python
Creates XML to front-end your own tools
</longdescription>
</pkgmetadata>

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# Copyright 1999-2020 Gentoo Authors
# Distributed under the terms of the GNU General Public License v2
EAPI=7
inherit autotools
DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
HOMEPAGE="https://www.veripool.org/wiki/verilator"
if [[ ${PV} == "9999" ]] ; then
inherit git-r3
EGIT_REPO_URI="https://git.veripool.org/git/${PN}"
else
SRC_URI="http://www.veripool.org/ftp/${P}.tgz -> ${P}.tar.gz"
KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sh ~sparc ~x86"
fi
LICENSE="|| ( Artistic-2 LGPL-3 )"
SLOT="0"
DEPEND="
dev-lang/perl
sys-libs/zlib
"
RDEPEND="
${DEPEND}
"
BDEPEND="
sys-devel/bison
sys-devel/flex
"
src_prepare() {
default
eautoconf --force
}